FIG. 1 is a block diagram of an example n-bit SAR DAC 10 that may be applied to embodiments of the present invention. The SAR DAC 10 includes a successive approximation register (SAR) logic circuit 102, a digital-to-analog converter (DAC) 104, and a voltage comparator 106. The DAC 104 weights an analog input signal Vin according to n digital data bits (D0, . . . , Dn−1) from the SAR logic circuit 102 and generates an analog output signal Vdac. The comparator 106 compares the analog output signal Vdac to an analog input signal Vin and provides a comparison result 16 to the SAR logic circuit 102. The SAR logic circuit 102 processes the comparison result successively in accordance with well-known successive approximation principles and outputs the digital output signals in a parallel form or in a serial form. The successive approximation process may be the following: the MSB bit is first initialized as 1, which is converted to an analog output signal Vdac by the DAC 104. The comparator 106 compares the signal Vdac to the analog input signal Vin, if Vin>Vdac, the MSB bit is set (logic 1 or high logic), if not, the MSB bit is set to 0 (zero or low logic), the next highest (MSB-1) bit is then set and the process repeats until the LSB bit is tested. The SAR logic circuit 102 then outputs digital output signals 105 after the end of the conversion (EOC) in a parallel form or in a serial form.
FIG. 2 is a conventional n-bit SAR ADC 20 including a binary weighted capacitor array DAC 204. Referring to FIG. 2, the binary weighted capacitor array DAC 204 includes a plurality of binary weighted capacitors C0, . . . , Cn-1, which are connected to the input voltage signal Vin for sampling. For example, if C0 is a capacitor having a unity capacitance value C, C1=2C, C2=4C, C3=8C, . . . , Cn−1=2n−1 C. The n-bit SAR ADC 20 also includes n switches S0, S1, S2, . . . , Sn−1, where n equals to the number of weighted capacitors in the binary weighted capacitor array. Each of the n switches controls the connection of a respective capacitor to a reference voltage Vref, to an input voltage Vin, or to a ground potential. During the sampling phase, the n switches are in position 1 and the n capacitors are connected to the input voltage Vin. During the holding phase and conversion phase, the n switches are either in position 2 or 3 in accordance with their respective digital data bits. For example, for the first switch S0, if its data bit D0 is a logic 0, the switch S0 is in position 3, and if the data bit D0 is a logic 1, the switch S0 is in position 2. Thus, the inputs to each of the capacitors C0 to Cn−1 is a binary weighted representation of the reference voltage Vref.
This implementation of the n-bit SAR ADC has significant drawbacks. For SAR ADC converters with high bit resolutions, the ratio between the MSB capacitor (i.e., Cn−1) and the LSB capacitor (i.e., C0) increases exponentially with the number of bits (i.e., resolution) due to the binary scaling. Further, the large capacitance value increases the silicon area needed for the weighted capacitor array, and the input capacitance during the sampling phase of operation. For example, the input capacitance of this implementation during the sampling phase is the sum of all n capacitors C0 to Cn−1 (i.e., C+2C+4C+ . . . +2n−1 C). Further, an n-bit SAR ADC requires that the MSB capacitor Cn−1 is 2n−1 times the value of the unit capacitor C. For example, a 10-bit SAR ADC requires that the MSB capacitor is 1023 times of the value of the unit capacitor. The large ratio between the unit capacitor and the MSB capacitor becomes too large to the point that its implementation is no longer feasible.
Thus, there is a need for a novel circuit and method to reduce the input capacitance and the silicon area that increase exponentially with the number of bits.